Display device and method of manufacturing the same

ABSTRACT

Provided are a display device and a method of manufacturing of the display device. The display device includes a substrate subjected to a primary preprocess; a conductor formed on the substrate and subjected to a secondary preprocess; and an insulating layer formed on the substrate and the conductor, in which the primary preprocess is performed for a surface energy of the first substrate higher than a first reference value and the secondary preprocess is performed for a surface energy of the conductor lower than a second reference value.

CROSS-REFERENCE TO RELATED APPLICATION

This application is a Divisional Application of U.S. patent applicationSer. No. 13/211,360, filed Aug. 17, 2011, and claims priority to and thebenefit of Korean Patent Application No. 10-2011-0027611, filed on Mar.28, 2011, both of which are incorporated herein by reference for allpurposes as if fully set forth herein.

BACKGROUND OF THE INVENTION

1. Field of the Invention

Exemplary embodiments of the present invention relate to a displaydevice and a method of manufacturing of the display.

2. Description of the Background

In recent years, as display devices, flat panel displays have spawnedsignificant adoption by consumers as an accepted mode of a display forbusiness and personal uses. Manufacturers have fueled this acceptance bydeveloping more enhanced display device for an application whichrequires a smaller size of a screen of a liquid crystal display and anorganic light emitting diode display.

The liquid crystal display typically includes a pixel including aswitching element implemented as a thin film transistor (TFT) which is a3-terminal element and a panel provided with display signal lines suchas a gate line and a data line.

The thin film transistor serves as the switching element that transfersor interrupts to a pixel a data signal through the data line accordingto a gate signal transferred through the gate line.

Unfortunately, as applications of the display devices demand both alarge display area and a high resolution, a signal delay such as an RCdelay may be inevitable, and as a result, the data signal cannot besufficiently charged in each pixel, thereby deteriorating a displayquality. Accordingly, technologies such as a low-resistance wire,increase in a wire thickness, a minute pattern, and the like arerequired to solve an RC delay. However, since an aperture ratio shouldnot be decreased, the increase in the wire thickness is necessarilyrequired as trade off for improving the aperture ratio.

On the other hand, in the case in which the wire thickness increases,steps of other layers to be positioned over the thick wires alsoincrease that causes a probability of defects such as disconnections.Further, when flatness is deteriorated due to the increase of the steps,the liquid crystal molecules may move abnormally, and as a result, theperformance of the liquid crystal display may be deteriorated.

Therefore, there is a need to improve flatness of a display.

The above information disclosed in this Background section is only forenhancement of understanding of the background of the invention andtherefore it may contain information that does not form the prior artthat is already known in this country to a person of ordinary skill inthe art.

SUMMARY OF THE INVENTION

These and other needs are addressed by the present invention, in whichexemplary embodiments of the present invention provide a display deviceand a method of manufacturing the same having advantages of improvingflatness of a display.

Exemplary embodiments of the present invention disclose a displaydevice. The display device includes a substrate having a first surfaceenergy. The display device also includes a conductor disposed on thesubstrate and having a second surface energy. The first surface energyis higher than the second surface energy and a peak to valley which is adifference between a maximum thickness corresponding to the conductorand a minimum tickness corresponding to the substrate associated withpatterning is minimized for an improved planarization.

Exemplary embodiments of the present invention disclose a method ofmanufacturing a display device. The method includes performing apreprocess to a substrate for a surface energy of the substrate. Themethod also includes disposing a conductive layer on the substrate. Themethod includes performing a preprocess to the conductive layer for asurface energy of the conductive layer lower than the surface energy ofthe substrate. The method also includes forming a conductor bypatterning the conductive layer. The method includes forming aninsulating layer on the substrate and the conductor.

Exemplary embodiments of the present invention disclose a display. Thedisplay includes a substrate having an attraction surface energy. Thedisplay also includes a conductor disposed on the substrate having arepulsion surface energy, a peak to valley thickness difference of aninsulating layer between a minimum thickness corresponding to a surfaceof the substrate and a maximum thickness corresponding to the surface ofthe conductor for a planarization is minimized.

Exemplary embodiments of the present invention disclose a method. Themethod includes performing a preprocess to increase surface energy of asubstrate using an attraction energy of interaction. The method alsoincludes disposing a conductive layer on the preprocessed substrate. Themethod includes a preprocess to decrease surface energy of theconductive layer using a repulsion energy of interaction. The methodincludes patterning a gate by forming the conductive layer.

It is to be understood that both the foregoing general description andthe following detailed description are exemplary and explanatory and areintended to provide further explanation of the invention as claimed.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a layout view illustrating a liquid crystal display accordingto exemplary embodiments of the present invention, and FIG. 2 is a crosssectional view illustrating the liquid crystal display taken along lineII-II of FIG. 1.

FIG. 3 and FIG. 4 illustrate surface energy when various preprocessesare performed on each substrate and conductive layer.

FIG. 5, FIG. 6, FIG. 7, FIG. 8, FIG. 9. FIG. 10, FIG. 11, FIG. 12, FIG.13 and FIG. 14 illustrate exemplary methods of manufacturing a lowerpanel of a liquid crystal display according to exemplary embodiments ofthe present invention.

FIG. 15, FIG. 16, FIG. 17, FIG. 18 and FIG. 19 illustrate exemplarymethods of manufacturing an upper panel of a liquid crystal displayaccording to exemplary embodiments of the present invention.

FIG. 20 is a flowchart of process for improving flatness of a displayusing a preprocess according to exemplary embodiments of the presentinvention.

DETAILED DESCRIPTION OF THE EMBODIMENTS

The invention is described more fully hereinafter with reference to theaccompanying drawings, in which embodiments of the invention are shown.This invention may, however, be embodied in many different forms andshould not be construed as limited to the embodiments set forth herein.Rather, these embodiments are provided so that this disclosure isthorough, and will fully convey the scope of the invention to thoseskilled in the art. In the drawings, the size and relative sizes oflayers and regions may be exaggerated for clarity. Like referencenumerals in the drawings denote like elements.

In the drawings, thickness of layers, films, panels, and regions may beexaggerated for clarity. Like reference numerals designate like elementsthroughout the specification. It will be understood that when an elementsuch as a layer, film, region, or substrate is referred to as being “on”another element, it can be directly on the other element or interveningelements may also be present. In contrast, when an element is referredto as being “directly on” another element, there are no interveningelements present.

FIG. 1 is a layout view illustrating a liquid crystal display accordingto exemplary embodiments of the present invention, and FIG. 2 is a crosssectional view illustrating the liquid crystal display taken along lineII-II of FIG. 1.

Referring to FIG. 1 and FIG. 2, for example, the liquid crystal displayincludes a lower panel 100 and an upper panel 200 facing each other anda liquid crystal layer 3 interposed between the two panels 100 and 200.Polarizers (not shown) may be disposed on the outer surfaces of thepanels 100 and 200.

First, the lower panel 100 will be described.

In this example, a gate conductor including a plurality of gate lines121 is formed on a substrate 110 made of transparent glass or aninsulating material such as plastic.

The gate line 121 transfers a gate signal, extends substantially in ahorizontal direction, and includes a plurality of gate electrodes 124protruding upwards and a wide end portion (not shown) for connectingother layer or a gate driver (not shown). When the gate driver (notshown) is integrated on the substrate 110, the gate line 121 extends tobe directly connected thereto.

The gate conductor 121 of FIG. 2 may be made of low-resistance metalsuch as an aluminum-based metal such as aluminum (Al) or an aluminumalloy, a silver-based metal such as silver (Ag) or a silver alloy, gold(Au), and a copper-based metal such as copper (Cu) or a copper alloy. Inaddition, the gate conductor 121 may have a multilayer structureincluding two conductive layers (not shown) having different physicalproperties. In addition, the gate conductor 121 may be made of variousmetals or conductors.

In order to reduce RC delay, a thickness h1 for the substrate 110 of thegate conductor 121 may be thickly formed. For example, the thickness h1of the gate conductor 121 may be 0.3 um to 2 um.

A gate insulating layer 140 is formed on the substrate 110 and the gateconductor 121. The gate insulating layer 140 may have a dual-layeredstructure including a first insulating layer 141 and a second insulatinglayer 142. In addition, the gate insulating layer 140 may have asingle-layered structure.

The first insulating layer 141 may be made of an organic insulator. Forexample, the first insulating layer 141 may be made of silsesquioxane(SSQ) such as hydrogen silsesquioxane (HSQ), methylsilsesquioxane (MSQ),or the like. In addition, the first insulating layer 141 may be made ofa high heat-resisting material. The first insulating layer 141 may notbe formed on the gate conductor 121.

The second insulating layer 142 is formed on the first insulating layer141 and the exposed gate conductor 121. For example, the secondinsulating layer 142 may be made of silicon nitride (SiNx), siliconoxide (SiOx), or the like.

The substrate 110 is subjected to a primary preprocess (circle mark) sothat surface energy of the substrate 110 is larger than a firstreference value and the gate conductor 121 is subjected to a secondarypreprocess (solidus mark) so that surface energy of the gate conductor121 is smaller than a second reference value. The surface energy of alayer, a film, an area, or a plate means a value converting a contactangel into energy after measuring each contact angle using a polarsolvent and a non-polar solvent for the surface of a layer, a film, anarea, or a plate. For example, the polar solvent may be H₂O and thenon-polar solvent may be CH₂I₂.

The first reference value may be the surface energy of the firstsubstrate 110 before performing the primary preprocess. When the firstsubstrate 110 is made of glass, the surface energy of the firstsubstrate 110 without performing the primary preprocess may be about 50J. The second reference value may be the surface energy of the gateconductive layer 120 before performing the secondary preprocess. Whenthe gate conductive layer 120 is made of a copper-based metal or thelike, the surface energy of the gate conductive layer 120 withoutperforming the secondary preprocess may be about 55 J.

The surface energy of the primary preprocessed substrate 110 may be 55 Jor more and the surface energy of the secondary preprocessed gateconductor 121 may be 30 J or less.

The surface energy of the primary preprocessed substrate 110 isincreased and the surface energy of the secondary preprocessed gateconductor 121 is decreased. Accordingly, the substrate 110 having highsurface energy has a high affinity with the first insulating layer 141and the gate conductor 121 having low surface energy has a low affinitywith the first insulating layer 141.

When the first insulating layer 141 is formed on the primarypreprocessed substrate 110 and the secondary preprocessed gate conductor121, the first insulating layer 141 may be thickly formed on thesubstrate 110 having high surface energy. On the other hand, the firstinsulating layer 141 may not be thickly formed on the gate conductor 121having low surface energy. Accordingly, a Peak to Valley (PV) which is adifference between a maximum thickness h1 and a minimum thickness h2 ofthe first insulating layer 141 may be reduced and the flatness of thefirst insulating layer 141 may be improved. As the Peak to Valley (PV)of the first insulating layer 141 is reduced, the flatness of the firstinsulating layer 141 may be improved. The flatness of the firstinsulating layer 141 may be 0.6 um or less. According to the exemplaryembodiments of the present invention, the Peak to Valley (PV) of thefirst insulating layer 141 which is formed on the primary preprocessedsubstrate 110 and the secondary preprocessed gate conductor 121 may bedecreased by about 20% or more as composed with the Peak to Valley (PV)without performing the primary preprocess and the secondary preprocess.

Hereinafter, the primary preprocess and the secondary preprocess will bedescribed with reference to FIG. 3 and FIG. 4.

FIG. 3 and FIG. 4 represent surface energy when various preprocesses areperformed on each substrate and conductive layer.

FIG. 3 is a graph illustrating surface energy of a substrate in the casewhere various primary preprocesses (i.e., primary preprocess No. 1 toNo. 12) are performed on the substrate, and FIG. 4 is a graphillustrating surface energy of a conductive layer in the case wherevarious secondary preprocesses (i.e., secondary process No. 1 to No. 12)are performed on the conductive layer. By way of example, the substrateof FIG. 3 is made of glass and the conductive layer of FIG. 4 is made ofa copper-based metal.

Referring to FIG. 3 and FIG. 4, the surface energy of the substratewithout performing the primary preprocess is about 50 J and in FIG. 9,the surface energy of the conductive layer without performing thesecondary preprocess is about 55 J.

The following Table illustrates each preprocess of the primarypreprocess and the secondary preprocess with respect to cases of No. 1to No. 12 of FIG. 3 and FIG. 4.

TABLE 1 Case Kind of preprocess No. 1 CF₄, 30 seconds, washing 0 timeNo. 2 CF₄, 30 seconds, washing 1 time No. 3 CF₄, 30 seconds, washing 3times No. 4 CF₄, 10 seconds, washing 0 time No. 5 CF₄, 10 seconds,washing 1 time No. 6 photoresist coating(Photoresist coating) No. 7HMDS(Hexamethyl-disilzane) 1 time No. 8 acid treatment No. 9 basetreatment No. 10 UV treatment No. 11 O₂ No. 12 brushing

In the above Table, for example, a preprocessing material of each casemay be preprocessed on the substrate and the conductive layer using aplasma enhanced chemical vapor deposition (PECVD) method. Thepreprocessing material is physically and chemically absorbed on thesurface of the substrate and the surface of the conductive layer throughthe preprocess and the surface energy of the substrate or the surfaceenergy of the conductive layer is changed.

In the above Table, for example, carbon tetrafluoride (CF₄) is used asthe preprocessing material in cases No. 1 to No. 5, but Sulfurhexafluoride (SF₆) instead of CF₄ may be used.

Referring to the above Table and FIG. 3, the primary preprocesses ofcases No. 2, No. 3, No. 5, and No. 8 to No. 12 increase the surfaceenergy of the substrate as compared with the case where the primarypreprocess is not performed on the substrate. Particularly, the surfaceenergy of the primary preprocessed substrate of cases No. 2, No. 3, No.5, No. 8, and No. 11 may be increased by about 60 J or more.

Accordingly, for example, the primary preprocess may be performed byprocessing one of SF₄, CF₄, and O₂ on the substrate through the PECVDmethod. When SF₄ or CF₄ is used as the primary preprocessing material,the substrate may be washed at least one time or more after SF₄ or CF₄is processed by the PECVD method. In this example, the preprocessingtime of the PECVD method may be 10 seconds or more.

Referring the above Table and FIG. 4, the secondary preprocesses of allthe cases except for the case No. 12 in which the secondary preprocessis brushing decrease the surface energy of the conductive layer ascompared with the case where the secondary preprocess is not performedon the conductive layer. In particular, the surface energy of thesecondary preprocessed conductive layer of cases No. 1, No. 8, and No.11 is deceased by about 30 J or less.

Accordingly, the secondary preprocess may be performed by processing oneof SF₄, CF₄, and O₂ on the conductive layer through the PECVD method oracid treatment. When SF₄ or CF₄ is used as the secondary preprocessingmaterial, SF₄ or CF₄ may be processed on the conductive layer throughthe PECVD method. In this example, the preprocessing time of the PECVDmethod may be 30 seconds or more and the conductive layer may be notwashed after being processed through the PECVD method.

The surface energy of the secondary preprocessed conductive layer is notlargely changed even after patterning using such as photolithography.

Referring back to FIG. 1 and FIG. 2, for example, a plurality of linearsemiconductors 151 made of hydrogenated amorphous silicon (a-Si is anacronym for amorphous silicon), or polysilicon are formed on the gateinsulating layer 140. Each linear semiconductor 151 extendssubstantially in a vertical direction and a plurality of semiconductors154 extend toward the gate electrode 124 from the linear semiconductor151.

Ohmic contacts 161 and 165 including a plurality of linear ohmiccontacts 161 and a plurality of island ohmic contacts 165 are formed onthe linear semiconductor 151. The linear ohmic contact 161 has aplurality of protrusion portions 163 and the protrusion portion 163 andthe island ohmic contact 165 are disposed on the semiconductor 154 byfacing each other based on the gate electrode 124 to make a pair. Theohmic contacts 161 and 165 may be made of a material such as n+hydrogenated amorphous silicon which is doped by an n-type impurity suchas phosphorus at the high concentration or silicide.

A data conductor including a plurality of data lines 171 and a pluralityof drain electrodes 175 is formed on the ohmic contacts 161 and 165.

The data line 171 transfers a data signal and extends substantially in avertical direction to cross the gate line 121. Each data line 171includes a plurality of source electrodes 173 which extend toward thegate electrode 124 to be bent in a U shape and a wide end portion (notshown) for connecting other layer or a data driver (not shown). When thedata driver (not shown) is integrated on the substrate 110, the dataline 171 extends to be directly connected therewith.

The drain electrode 175 is separated from the data line 171 and facesthe source electrode 173 based on the gate electrode 124. A part of thedrain electrode 175 is surrounded by the bent source electrode 173.

The data conductors 171 and 175, for example, may be made of arefractory metal such as molybdenum, chromium, tantalum, and titanium oran alloy thereof and have a multilayer structure including a refractorymetal layer (not shown) and a low-resistance conductive layer (notshown). In addition, the data conductors 171 and 175 may be made of thesame kind of metal as the gate conductor 121.

A portion disposed at an interface of the gate conductor 12 among thelinear semiconductor 151, the ohmic contacts 161 and 165, and the dataconductors 171 and 175 have a gentle slope. This is because the slope ofthe lower gate insulating layer 140 is gentle. The linear semiconductors151, the ohmic contacts 161 and 165, and the data conductors 171 and 175are not sharply changed in heights due to the gate insulating layer 140having the gentle slope, thus a defective such as disconnection may beprevented.

The gate electrode 124, the semiconductor 154, the source electrode 173,and the drain electrode 175 form a thin film transistor (TFT) Q. Achannel of the thin film transistor is formed at the semiconductor 154between the source electrode 173 and the drain electrode 175.

As described above, the first insulating layer 141 among the gateinsulating layers 140 may not be formed on the gate conductor 121.Accordingly, the first insulating layer 141 is not at the channelportion of the thin film transistor. Therefore, since only the secondinsulating layer 142 is disposed between the gate electrode 124 and thesemiconductor 154, a distance between the gate electrode 124 and thechannel is prevented from being far away from each other such that aproperty of the thin film transistor is not deteriorated.

The linear semiconductor 151 including the semiconductor 154 has nearlythe same plane shape as the data line 171, the drain electrode 175, andthe ohmic contacts 161 and 165 therebelow, except for the channel areabetween the source electrode 173 and the drain electrode 175. Accordingto exemplary embodiments, the ohmic contacts 161 and 165 havesubstantially the same plane shape as the data line 171 and the drainelectrode 175, but the linear semiconductor 151 has an exposed portionbetween the source electrode 173 and the drain electrode 175 withoutbeing covered by the data conductors 171 and 175 and the ohmic contacts161 and 165.

For example, a passivation layer 180 is formed on the data conductors171 and 175 and the exposed portion of the semiconductor 154. Thepassivation layer 180 may be made of an inorganic insulator or anorganic insulator.

A contact hole 185 exposing the drain electrode 175 is formed at thepassivation layer 180.

A plurality of pixel electrodes 191 are formed on the passivation layer180. The pixel electrode 191 may be made of a transparent conductor suchas indium-tin-oxide (ITO), or indium-zinc-oxide (IZO), as an example.

The pixel electrode 191 is entirely a quadrangle and is connected withthe drain electrode 175 through the contact hole 185. When the thin filmtransistor is turned on, the pixel electrode 191 receives the datasignal from the drain electrode 175.

For example, an alignment layer 11 is formed on the pixel electrode 191and the passivation layer 180. The alignment layer 11 may be a verticalalignment layer.

In FIG. 2, the lower panel 100 where the data conductors 171 and 175 areformed on the gate conductor 121 is described as an example, but theexemplary embodiments of the present invention may be also applied atthe lower panel having a top gate structure where the gate conductor isformed on the data conductor. That is, in the lower panel having the topgate structure, the insulating layer is formed on the primarypreprocessed substrate increasing the surface energy and the secondarypreprocessed data conductor decreasing the surface energy to improve theflatness of the insulating layer. In addition, the gate conductor may beformed on the insulating layer having improved flatness.

For example, the secondary preprocess according to exemplary embodimentsof the present invention can be also applied at other conductors such asthe data conductor in addition to the gate conductor. The surface energyof the substrate can be increased and the surface energy of theconductor can be decreased through the primary preprocess on thesubstrate and the secondary preprocess on the conductor disposed abovethe substrate. As a result, the flatness of the insulating layer formedon the substrate and the conductor can be improved.

Next, the upper panel 200 will be described.

The upper panel 200 has a light blocking member 220 which is formed on asubstrate 210 made of an insulating material such as transparent glassor plastic. The light blocking member 220 referred as a black matrix isprovided to prevent light leakage between the pixel electrodes 191. Forexample, the light blocking member 220 includes a plurality of openings221 facing the pixel electrode 191 and having nearly the same shape asthe pixel electrode 191.

A plurality of color filters 230 are formed on the substrate 210 and thelight blocking member 220. The color filters 230 are mostly in theopenings 221 of the light blocking member 220. Each color filter 230 maydisplay one of three primary colors such as red, green and blue.

The light blocking member 220 is subjected to a tertiary preprocess (xmark) so that the surface of the light blocking member 220 has arepellence for the color filter 230. The plurality of openings 221 areformed by etching the tertiary preprocessed light blocking member 220.For example, color materials including pigments are coated in each ofthe plurality of openings 221 of the light blocking member 220 by aninkjet printing method to form the color filter 230.

The light blocking member 220 is tertiary-preprocessed so that thesurface of the light blocking member 220 has a high repellence for thecolor materials, before forming the openings 221. For example, when thecolor material is a hydrophilic material, the surface of the lightblocking member 220 may be subjected to preprocess so as to have ahydrophobic property through the tertiary preprocess. In this example,the light blocking member 220 may be subjected to the tertiarypreprocess with the hydrophobic material by the PECVD method.

Since the openings 221 are formed at the light blocking member 220 afterthe tertiary preprocess, the side of the light blocking member 220 wherethe openings 221 are formed and the surface of the substrate 210 wherethe openings 221 are exposed do not have the hydrophobic property andonly the surface of the light blocking member 220 has the hydrophobicproperty.

The color material is repelled with the surface of the light blockingmember 220 through the tertiary preprocess and the color material iscoated only in the openings 221 of the light blocking member 220, suchthat the color filter 230 can be formed only in the openings 221.

Unlike in FIG. 2, for example, the light blocking member 220 and thecolor filter 230 may be formed on the lower panel 100.

An overcoat 250 is formed on the light blocking member 220 and the colorfilter 230. The overcoat 250 may being made of an insulator, preventsthe color filter 230 from being exposed, and provides a flat surface.The overcoat 250 may be omitted to avoid unnecessarily obscuring thepresent invention.

For example, a common electrode 270 is formed on the overcoat 250. Thecommon electrode 270 is made of a transparent conductor such as ITO orIZO and receives common voltage Vcom. An alignment layer 21 may beformed on the common electrode 270. The alignment layer 21 may be avertical alignment layer.

The liquid crystal layer 3 interposed between the lower panel 100 andthe upper panel 200 includes liquid crystal molecules having dielectricanisotropy and in the state in which no electric field is applied, theliquid crystal molecules may be aligned so that the long axis thereof isperpendicular to the surfaces of the two panels 100 and 200.

The pixel electrode 191 applied with the data signal generates anelectric field together with the common electrode 270 of the upper panel200 to determine a direction of the liquid crystal molecules of theliquid crystal layer 3 between the two electrodes 191 and 270. Accordingto the inclined degree of the liquid crystal molecules, variation inpolarization of light inputted into the liquid crystal layer 3 variesand the variation of polarization is shown as variation in transmittanceby a polarizer, such that the liquid crystal display displays the image.

As such, steps between other layers to be disposed above the firstinsulating layer 141 by the thick gate conductor 121 may be preventedfrom being increased by improving the flatness of the first insulatinglayer 141 through the primary preprocessed (circle mark) substrate 110and the secondary preprocessed (solidus mark) gate conductor 121.Accordingly, the defective such as disconnection may be prevented frombeing generated at the other layers disposed above the first insulatinglayer 141.

In addition, since the flatness of the lower panel 100 is entirelyimproved, nonideal (e.g., mischarateristic) behaviors of the liquidcrystal molecules can be prevented consequently performance of theliquid crystal display is improved.

In addition, the color filter 230 can be formed only in the openings 221of the light blocking member 220 through the tertiary preprocessed (xmark) light blocking member 220 increasing the repellence between thecolor material and the surface of the light blocking member 220.

Hereinafter, a method of manufacturing a liquid crystal displayaccording to exemplary embodiments of the present invention will bedescribed with reference to FIG. 5 to FIG. 19.

FIG. 5 to FIG. 14 illustrate exemplary methods of manufacturing a lowerpanel of a liquid crystal display according to exemplary embodiments ofthe present invention.

First, referring to FIG. 5 and FIG. 6, a substrate 110 made of aninsulating material such as transparent glass or plastic is subjected toa primary preprocess. Surface energy of the primary preprocessed (circlemark) substrate 110 is increased as compared with a first referencevalue.

Referring to FIG. 7, for example, a gate conductive layer 120 is stackedon the primary preprocessed substrate 110 with a low-resistance metalsuch as an aluminum-based metal, a silver-based metal, and acopper-based metal. A thickness h1 of the gate conductive layer 120 maybe about 0.3 um to about 2 um.

By way of example, the gate conductive layer 120 may be stacked by usinga sputtering, an electroplating, an electroless plating, an inkjetprinting, and a gravure printing methods.

Referring to FIG. 8 and FIG. 9, the gate conductive layer 120 issubjected to a secondary preprocess. Surface energy of the secondarypreprocessed (solidus mark) gate conductive layer 120 is decreased ascompared with a second reference value.

Referring to FIG. 10, the secondary preprocessed gate conductive layer120 forms gate conductors 121 and 124 including a plurality of gatelines 121 and a plurality of gate electrodes 124 protruding from thegate line 121 by patterning using photolithography.

Referring to FIG. 11, a first insulating layer 141 is stacked on theprimary preprocessed substrate 110 and the secondary preprocessed gateconductors 121 and 124.

When the first insulating layer 141 is formed on the primarypreprocessed substrate 110 and the secondary preprocessed gate conductor121, the first insulating layer 141 may be thickly formed on thesubstrate 110 having high surface energy. On the other hand, the firstinsulating layer 141 cannot be thickly formed on the gate conductor 121having low surface energy. Accordingly, a thickness h4 of the firstinsulating layer 141 stacked just on the substrate 110 is larger than athickness h3 of the first insulating layer 141 stacked just on the gateconductors 121 and 124. Therefore, a peak to valley which is adifference between the maximum thickness h1+h3 and the minimum thicknessh4 of the first insulating layer 141 can be decreased and flatness ofthe first insulating layer 141 is improved.

Referring to FIG. 12, for example, the first insulating layer 141 isetched until the gate conductors 121 and 124 are exposed. As shown inFIG. 11, since the peak to valley of the first insulating layer 141 isnot large before etching, a peak to valley (PV) which is a differencebetween the maximum thickness h1 and the minimum thickness h2 of thefirst insulating layer 141 can be decreased even after the etching.

Referring to FIG. 13, a second insulating layer 142 is stacked on thefirst insulating layer 141 and the exposed gate conductors 121 and 124.As such, the gate insulating layer 140 may be formed as a dual-layeredstructure including the first insulating layer 141 and the secondinsulating layer 142. However, the gate insulating layer 140 may beformed as a single-layered structure, and in this example, the etchingprocess of the first insulating layer 141 and the stacking process ofthe second insulating layer 142 in FIG. 12 may be omitted to avoidunnecessarily obscuring the present invention.

A semiconductor layer 150 and a semiconductor layer 160 doped with animpurity are sequentially stacked on the gate insulating layer 140 usinga chemical vapor deposition method. Subsequently, the data conductivelayer 170 is stacked by a sputtering method. As such, steps between thesemiconductor layer 150, the semiconductor layer 160 doped with animpurity, and the data conductive layer 170 may be prevented from beingincreased by providing the high flatness of the gate insulating layer140 through the primary preprocess and the secondary preprocess.Accordingly, the defective such as disconnection may be prevented at theother layers 150, 160, and 170 disposed above the gate insulating layer140.

Referring to FIG. 14, for example, a plurality of data conductors 171and 175, a plurality of ohmic contacts 161 and 165, a plurality oflinear semiconductors 151 are formed by etching the data conductivelayer 170 and the semiconductor layer 160 doped with an impurity.

Next, a plurality of contact holes 185 are formed by etching after thepassivation layer 180 is formed by coating or stacking an organicinsulating material or an inorganic insulating material. Next, aplurality of pixel electrodes 191 are formed by depositing andpatterning an IZO or ITO layer on the passivation layer 180 using asputtering method. Finally, an alignment layer 11 is formed bydepositing a material such as polyimide-based polymer on the passivationlayer 180. As a result, the lower panel 100 of FIG. 2 can bemanufactured.

FIG. 15 to FIG. 19 illustrate exemplary methods of manufacturing anupper panel of a liquid crystal display according to exemplaryembodiments of the present invention.

Referring to FIG. 15 to FIG. 18, a light blocking member 220 issubjected to a tertiary preprocess on a substrate 210 made of aninsulating material such as transparent glass or plastic. A plurality ofopenings 221 are formed by etching the tertiary preprocessed (x mark)light blocking member 220. Next, color materials including pigments arecoated in each of the plurality of openings 221 of the light blockingmember 220 by an inkjet printing method to form the color filter 230.The repellence between the surface of the light blocking member 220 andthe color material is increased through the tertiary preprocess.Accordingly, the color filter 230 can be formed only in the openings 221of the light blocking member 220.

Referring to FIG. 19, for example, an overcoat 250 is formed by coatingor stacking an insulating material on the light blocking member 220 andthe color filter 230, a common electrode 270 is formed by depositing anITO or IZO layer on the overcoat 250 using a sputtering method, and analignment layer 21 is formed by depositing a material such aspolyimide-based polymer on the common electrode 270. As a result, theupper panel 200 of FIG. 2 can be manufactured.

Therefore, a display device having improved flatness and a method ofmanufacturing the same can be provided.

The flatness of the insulating layer can be improved using the primarypreprocessed substrate to increase the surface energy and using thesecondary preprocessed conductor to decrease the surface energy.Accordingly, a number of steps required between other layers to bedisposed above the insulating layer caused by a thick conductor can beoptimally decreased. Therefore, a defective characteristic such as adisconnection can be prevented from being generated associated with theother layers disposed above the insulating layer. In addition, since theflatness of the entire panel is improved due to the insulating layerhaving the improved flatness, nonideal behaviors of the liquid crystalmolecules can be prevented, thus preventing the liquid crystal displayfrom being deteriorated.

Further, the color filter can be formed only in the openings of thelight blocking member through the tertiary preprocessed light blockingmember that increase the repellence between the color material and thesurface of the light blocking member.

FIG. 20 is a flowchart of process for improving flatness of a displayusing a preprocess according to exemplary embodiments of the presentinvention.

As described, for example, as in step 500, performing a primarypreprocess to a substrate to increase a surface energy of the substratehigher than a first reference value. In step 501, disposing a conductivelayer on the substrate. The first reference value comprises a valueprior to a preprocess being applied on the substrate. In step 503,performing a secondary preprocess to the conductive layer to decrease asurface energy of the conductive layer lower than a second referencevalue. The second reference value comprises a value prior to apreprocess being applied on the conductor. The method also includesforming a conductor by patterning the conductive layer, and forming aninsulating layer on the substrate and the conductor.

According to exemplary embodiments, the method includes performing apreprocess to increase surface energy of a substrate using anattraction. The method also includes disposing a conductive layer on thepreprocessed substrate. The method includes performing a preprocess todecrease surface energy of the conductive layer using a repulsion. Andthe method includes patterning a gate by forming the conductive layer.

It will be apparent to those skilled in the art that variousmodifications and variations can be made in the present inventionwithout departing from the spirit or scope of the invention. Thus, it isintended that the present invention cover the modifications andvariations of this invention provided they come within the scope of theappended claims and their equivalents.

What is claimed is:
 1. A display device, comprising: a substrate; aplurality of gate electrodes on the substrate; a first insulating layerdisposed between the gate electrodes; and a second insulating layerdirectly contacting a top surface of the gate electrodes, wherein a peakto valley thickness difference of the first insulating layer is adifference between a maximum thickness corresponding to the gateelectrodes and a minimum thickness corresponding to the substrate. 2.The display device of claim 1, wherein the substrate has a first surfaceenergy; and the gate electrodes have a second surface energy, whereinthe first surface energy is higher than the second surface energy. 3.The display device of claim 2, wherein the first surface energy and thesecond surface energy represent based on each respective referencevalue, the reference value of the first surface energy comprises a valueprior to a preprocess being applied on the substrate, and the referencevalue of the second surface energy comprises a value prior to apreprocess being applied on the conductor.
 4. The display device ofclaim 3, wherein the first surface energy comprises about 55 J or moreand the second surface energy comprises about 30 J or less.
 5. Thedisplay device of claim 2, wherein the first surface energy is performedby processing one of SF₆, CF₄, or O₂ on the substrate by a plasmaenhanced chemical vapor deposition (PECVD) method.
 6. The display deviceof claim 5, wherein the second surface energy is performed by processingone of SF₆, CF₄ or O₂ on the conductor by the PECVD method.
 7. Thedisplay device of claim 1, wherein the peak to valley thicknessdifference of the first insulating layer is about 0.6 um or less.
 8. Thedisplay device of claim 1, further comprising: an another substrate; alight blocking member including openings on the another substrate; and acolor filter at the opening, wherein the surface of the light blockingmember except for the openings comprises a repellence with the colorfilter.
 9. The display device of claim 1, wherein the first insulatinglayer is disposed continuously between adjacent ones of the gateelectrodes.
 10. The display device of claim 1, wherein the secondinsulating layer is disposed on the first insulating layer.
 11. Thedisplay device of claim 10, wherein the second insulating layer directlycontacts the first insulating layer.
 12. The display device of claim 1,wherein the first insulating layer does not cover the top surface of thegate electrodes.
 13. The display device of claim 1, further comprising:a semiconductor disposed on the second insulating layer.